CSE

Dr. Jimson Mathew

Dr. Jimson Mathew
Associate Professor
PhD, University of Bristol, UK
Ph: +91-612-302 8347
jimson[*AT]iitp.ac.in
Research Areas
  • Fault Tolerant Computing, VLSI.
  • Design and Methodologies, Reliability Aware
  • Designs, Hardware Security etc.
PhD Students

Rakesh Kumar Sanodiya

Alwyn Mathew

Surjeet Singh Yadav
Awards & Honours
  • Dorothy Hodgkin Doctoral Fellowship, UK
  • Best Paper Award: International Conference on Embedded Systems
  • Mobile Communication and Computing, 2006
Member of Professional bodies Senior Member IEEE, Member IET
Books
  • V Mistra, Jimson Mathew, Lau Chiew Tong “QoS and Energy management in Cognitive Radio Networks” Springer DE, Germany, 2017, ISBN 978-3-319-45860-1.
  • Jimson Mathew, R. A. Shafik, Dhiraj Pradhan, “Energy Efficient Fault-Tolerant Systems”, Springer USA, ISBN 978-1-4614-4192-2 .2014
  • R. Remesan, Jimson Mathew, Hydrological Data Driven Modelling: A Case study Approach, Springer, USA, ISBN 978-3-319-09234-8, 2014.
  • Jimson Mathew, Patra P., Dhiraj Pradhan, Kuttyamma, A.J, Eco-friendly Computing and Communication Systems. . ISBN 978-3-642-32111-5. August 2012.
Patents
  • “Static Random Access Memory”, U.S. Patent No. 7706174; , 2010 (with J Singh, D K Pradhan)
  • “Novel Cross Parity Based Error Tolerant Circuit Design”, US Patent file No. 61/608,694, 2012(with P Mahesh, A,M Jabir, D K Pradhan).
  • "Circuits and Methods for Memristor based Physically Unclonable Function" US patent filed. File number 14948617, EFS ID 24159695, 23 November 2015(with R S. Chakraborty, Y Yang, A M Jabir, D. K Pradhan)
  • “BCH Code Based Error Tolerant Electronic Circuit Design”, Patent No. file 1114831.9,, 2011 (with P Mahesh, A,M Jabir, D K Pradhan).
  • "Circuit and Method for Read/Write in Complementary Resistive Switch Crossbar Memory" US patent filed. File number 14879297, 23 November 2015(with Y Yang, M. Ottavi, D K Pradhan)
  • “Circuit and Method for Embedding Fault Detection in Photovoltaic Arrays using Memristive Sensing ".US provisional patent filed, Application Number 62234103, 29 September 2015(with M, Ottavi, T Brown, Y. Yang)
Publications Refereed Journals
  • Rajat S. S, Sam P. Jimson Mathew, “A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis” IEEE Transactions on Emerging Topics in Computing, (2017).
  • J. Prakash A V, B. R. Jose,E, Jimson Mathew, B. A Jose ,A Differential Quantizer based Error Feedback Modulator for Analog to Digital Converters, IEEE Transactions on Circuits and Systems II: Volume: PP, Issue: 99 )
    DOI: 10.1109/TCSII.2017.2666822 09 February 2017.
  • M. I. Bandan, S. Pagliarini, Jimson Mathew, and D. K Pradhan, Improved Multiple Faults-Aware Placement Strategy: Reducing the overheads and Error rates in Digital Circuits” IEEE Transactions on Reliability, ISSN: 0018-9529, Volume: 66, Issue: 1, March 2017 )
  • S. C. Rajat, R. R. Jeldi. I. Saha and Jimson Mathew, Binary Decision Diagram Assisted Modeling of FPGA-based Physically Unclonable Function by Genetic Programming, IEEE Transactions on Computers, 26 August 2016
    DOI: 10.1109/TC.2016.2603498
  • J Jacob, B.R. Jose, Jimson Mathew, "An Antenna Selection Scheme with MRE and AWC for Decision Fusion in Cognitive Radio"Transactions on Emerging Telecommunications Technologies (2017)
    DOI: 10.1002/ett.3161, Wiley.
  • C Abraham, B R Jose, Jimson Mathew, M. Evzelman,"Modelling, Simulation and Experimental investigation of a New Two Input, Series Parallel Switched Capacitor Converter" IET Power Electronics,
    DOI: 10.1049/iet-pel.2015.1000, 02 March 2017 Volume: 10, Issue: 3, 3 10 2017)
  • A Differential Quantizer based Error Feedback Modulator for Analog to Digital Converters By Jos Prakash A V, B. R. Jose,E, Jimson Mathew, B. A Jose , IEEE Transactions on Circuits and Systems II, 09 February (2017).
  • X. Yang, A. A. Adeyemo, A. Jabir, Jimson Mathew, High-performance single-cycle memristive multifunction logic architecture, Electronics Letters, 1-2 April (2016).
  • J Jacob, B R Jose, Jimson Mathew, Bayesian Analysis of spectrum occupancy prediction in Cognitive Radio, Smart Science, (Tailor and Francis), 19 May 2016.
    http://dx.doi.org/10.1080/23080477.2016.1182360
  • Y. Yang, Jimson Mathew, R. S. Chakraborty, M. Ottavi and D. K. Pradhan, Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications, IEEE Transactions on Nanotechnology, TNANO.2016.2553438, Vol.15, NO.3, May (2016).
  • Jimson Mathew, R. Chakraborty, D. K Pradhan, “ A Novel Memristor based Hardware Security Primitive, ACM Transactions on Embedded Computing Systems, 2015.
  • Y Yang, Jimson Mathew D. K. Pradhan, M. Ottavi and S. Pontarelli, “Complementary Resistive Switch Based Arithmetic Logic Implementations Using Material Implication, IEEE Transactions on Nanotechnology, 2015 .
  • Jimson Mathew, R. Chakraborty, D. K Pradhan, “A Novel Memristor based Physically Unclonable Function” Integration, the VLSI Journal – Elsevier (2015).
  • R. A Shafik, Jimson Mathew, D. K Pradhan A Low-Cost Unified Design Methodology for Secure Test and IP Core Protection’ IEEE Transactions on Reliability Special Section on Trustworthy Computing, 2015.
  • R. Remesan, M. Bray, Jimson Mathew, "Application of PCA and Clustering methods in Input Selection of Hybrid Runoff Models" Journal of Environmental Informatics, 2015.
  • C. Abraham, B. R. Jose, and Jimson Mathew, "A dual source switched-capacitor converter with solar energy integration capability" Int. J. Energy Technology and Policy (2015)
  • C. Abraham, B. R. Jose, and Jimson Mathew, “ A Multiple Input Variable Output Switched Capacitor DC–DC Converter for Harnessing Renewable Energy and Powering LEDs, Journal of Low Power Electronics, Vol. 11, 1–11, 2015
  • Gang G., Jimson Mathew, R. A. Shafik, D. K. Pradhan, M. Ottavi and S. PontarelliLifetime Reliability Analysis of Complementary Resistive Switches under Threshold and Doping Interface Speed Variations, IEEE Transactions on Nanotechnology, 2014 .
  • Y Yang., Jimson Mathew, D. K. Pradhan, M. Ottavi and S. PontarelliLifetime Novel Complementary Resistive Switch Crossbar Memory Write and Read Schemes , IEEE Transactions on Nanotechnology, 2014 .
  • Mahesh. P, Jimson Mathew, A. Jabir, D. K. Pradhan, “A Low Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2^m)”, IEEE Transactions on Very Large Scale Integration Systems, IEEE TVLSI 2014..
  • Y. Yang, Jimson Mathew, R A Shafik, Dhiraj Pradhan, Verilog-A based Effective Complementary Resistive Switch Model for Simulations and Analysis. IEEE Embedded Systems Letters,2014.
  • Gang Lia, Jimson Mathew, Rishad Shafik and Dhiraj Pradhan Multinomial based memristor modelling methodology for simulations and analysis, Journal of Electronics, Tailor and Francis, UK, 2014.
  • Jimson Mathew, S. Mohanty, D.K Pradhan, “Attack Tolerant Cryptographic Hardware Design by Combining Error Correction and Uniform Switching Activity”, Elsevier Computers and Electrical Engineering , 2014.
  • Y Yang, Jimson Mathew, , D. K. Pradhan “2T2M MTCAM Cell for Low-Power Embedded Systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems(under revision), 2014.
  • Mohamad B., Subhasis B., D. Pradhan Jimson Matthew Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System, Journal of Low Power Electronics, No. 10 September 2014.
  • L. Sun, Jimson Mathew, D K Pradhan, Design and Analysis of Binary Tree SRAM for Low Power Embedded Systems, Journal of Low Power Electronics, No. 10 September 2014.
  • V Mishra, LC Tong, S Chan, Jimson Mathew, "TQCR-media access control: two-level quality of service provisioning media access control protocol for cognitive radio network" IET Digital Library, 2014
  • Reddy, B.K., Sabbavarapu, S., Acharyya, A., Shafik, R.A. Jimson Mathew, "Novel IC Design Methodology Using Dynamic Library Concept with Reduced NRE Cost and Time-to-Market, Journal of Low Power Electronics, No. 10 September 2014.
  • L. Sun,, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, “Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits. Journal of Low Power Electronics (JOLPE), 8(3), pp. 261–269. January 2012.
  • V Mishra, C Tong Lau, S Chan, Jimson Mathew "Energy aware spectrum decision framework for cognitive radio network: a spectrum decision framework for cognitive radio network with energy awareness Journal of Low Power Electronics 9 (3), 313-321, 2013.
  • Narayanan, V.K, Shafik, R.A, Jimson Mathew, Dhiraj Pradhan, Fault Tolerant High Performance Galois Field Arithmetic Processor. Lecture Notes in Computer Science, . August 2012.
  • Jimson Mathew, K. Maharatna, H. Rahaman, D.K.Pradhan. ” Pseudo-parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for Wireless Personal Area Networks, Journal of Circuits and Systems” Journal of Embedded Signal Processing Circuits and Systems for Cognitive Radio-based Wireless Communication Devices (Springer) 2011 .
  • Jaison Jacob, Babita R. Jose, Jimson Mathew: Cellular Automata Approach for a Low Power Fusion Center to Evaluate Spectrum Status and Coverage Area in Cognitive Radios. J. Low Power Electronics 9(3): 332-339 (2013)
  • S. Banerjee, Jimson Mathew, S.P. Mohanty, Dhiraj Pradhan, M. Ciesielski, A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. Journal of Low Power Electronics, 7(4), pp. 471–481. December 2011.
  • S. Banerjee, Jimson Mathew, D.K. Pradhan, B. B. Bhattacharya, and S. P. Mohanty, “A Routing-Aware ILS Design Technique”, IEEE Transactions on Very Large Scale Integration Systems 2011.
  • B.R. Jose, Jimson Mathew, P.Mythili, ``A Multi-mode Sigma-delta ADC for GSM/WCDMA/WLAN Applications, ''Journal of Signal Processing Systems (Springer), Volume 62, Number 2, 117-130, DOI: 10.1007/s11265-008-0326-z Jan. 2011.
  • V. Misra, Jimson Mathew, Dhiraj Pradhan, Fault-tolerant De-Bruijn Graph Based Multipurpose Architecture and Routing Protocol for WSN. International Journal of Sensor Networks (IJSNet), . May 2011
  • H. Rahman, Jimson Mathew, D.K Pradhan “Test Generation in Systolic Architecture for Multiplication over GF(2^m)” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue 9.pp. 1366 - 1371, Sept. 2010.
  • Jimson Mathew, A.M. Jabir, , H. Rahaman, D. Pradhan, A Galois Field Based Logic Synthesis Approach with Testability. IET Proc. Part-E: Comp. Digital Tech. volume. 4, Issue. 4, pp. 263-273. July 2010.
  • S. Talapatra. H. Rahaman, Jimson Mathew, , Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Classes of GF(2^m)”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE TVLSI), Issue: 5, pages:847-852 May 2010.
  • H. Rahman, Jimson Mathew, D.K Pradhan Simplified Bit Parallel Systolic Multipliers for Special Class of GF(2m) with Testability, IET Computers & Digital Techniques” Volume : 4 , Issue:5, pp- 428- 427, July, 2010.
  • M. Hosseinabady, R. Kakoee, Jimson Mathew, Dhiraj Pradhan, "Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph". IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue 99.pp. 1-12, June 2010.
  • Jmson Mathew, A. M. Jabir and D.K Pradhan “Single Error Correctable Bit Parallel Multipliers Over GF(2^m)” IET Computers & Digital Techniques” Page(s): 281 – 288, Issue. 3, April 2009.
  • Jimson Mathew, R. Mahesh. A.P Vinod and L. Edmund, “Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Volume E91-A Issue 9, September 2008
  • A. Abu Taleb, Jimson Mathew C. Taskin, Dhiraj Pradhan, A Novel Fault Diagonosis Technique in Wireless Sensor Networks. International Journal On Advances in Telecommunications. Mar 2010.
  • Jimson Mathew, Jabir, A. M. , Rahaman, H. , Argyrides, C. and Pradhan, Dhiraj K."On the synthesis of bit-parallel Galois field multipliers with on-line SEC and DED", International Journal of Electronics, 96: 11, 1161 —1173, 2009.
  • D. Maslov, Jimson Mathew, D. Cheung, and Dhiraj K. Pradhan. “On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography, Journal of Quantum Information and Computation Vol.9 No.7&8 , July 1, 2009.
  • R. Remesan, D. Han. Jimson Mathew "Runoff Prediction Using an Integrated Hybrid Modelling Scheme. Journal of Hydrology (Elsevier). Vol. 372 No. 1/4 pp. 48-60, 2009.
  • A. K. Singh, Asish Bera, H. Rahaman, Jimson Mathew, and D.K.Pradhan “Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)” Journal of Electronic Science and Technology, 2009.
  • H. Rahaman, Jimson Mathew, Dhiraj Pradhan and A. M. Jabir. “C-Testable Bit Parallel Multipliers Over GF(2m)”. ACM Transactions on Design Automation of Electronic Systems (TODAES) Volume 13 Issue 1,pages.5:2-5:18, January 2008.
  • A. Jabir, Dhiraj Pradhan and Jimson Mathew. Gfxpress: An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m). IEEE Transactions on Computer Aided Design, (IEEE TCAD), Vol. 27, Issue 4, pages 698-711, March 2008.
  • D. Maslov, Jimson Mathew, Donny Cheung, and Dhiraj K. Pradhan. “On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography”, Lecture Notes in Computer Science (LNCS), 2008.
  • B.R Jose, , P. Mythili, Jimson Mathew GA-based Optimization of Sigma-delta Modulators for Wireless Transceivers Engineering Letters, Volume 16 Issue 4, Pages 473-479
  • H. Rahaman, Jimson Mathew, and D. K. Pradhan, “Derivation of Reduced Test Vectors for Bit Parallel Multipliers over GF(2^m)" IEEE Transactions on Computers (IEEE TC), vol. 57, Issue.9, Page(s): 1289 – 1294, 2008.
  • B.R. Jose, Mythili P. Jimson Mathew, “Dual-Band Sigma-delta ADC for WCDMA/WLAN Receivers”, International Journal of Applied Engineering Research, March 2008.
  • B.R. Jose, Mythili P. Jimson Mathew Sigma-Delta Analog to Digital Converter for WLAN with RNS based Decimation Filter, IETECH Journal of Information Systems, International Engineering and Technology Publications, Vol. 2, No. 2, pp. 68-75, 2008
  • H. Rahaman, Jimson Mathew, A. K Singh, B. K. Sikdar, Dhiraj K. Pradhan: Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m} Transactions on Circuit and Systems, 2008.

Refereed conferences:
  • A.Adeyemo, X.Yang, A.Bala , Jimson.Mathew , A.Jabir, “Analytic Models for Crossbar Read Operation”, 22nd IEEE International Symposium on On-Line Testing and Robust System Design,Catalunya, Spain, July 4-6, 2016.
  • Jimson Mathew, Y Yang, Marco O. D.K Pradhan, “Fault Detection and Repair of DSC Arrays through Memristor Sensing, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, USA, 2015.
  • A. Adeyemo Jimson Mathew, A. M Jabir, D.K Pradhan, “Exploring Error-Tolerant Low-Power Multiple-output Read Scheme for Memristor-Based Memory Arrays, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, USA, 2015.
  • J. Prakash, B R Jose, Jimson Mathew"A Novel Excess Sturdy-MASH-Loop-Delay Compensated Cross-Coupled ΣΔ Modulator"29th International Conference on VLSI Design (VLSI Design 2016), 4-8 January 2016, Kolkata, India. IEEE Computer Society 2008, ISBN 0-7695-3083-4
  • U Urbi, R S Chakraborthy, D. K PRadhan"Memristor based Arbiter PUF: Cryptanalysis Threat and its Mitigation"29th International Conference on VLSI Design (VLSI Design 2016), 4-8 January 2016, Kolkata, India. IEEE Computer Society , ISBN 0-7695-3083-4
  • Jimson Mathew, Y Yang, Marco O. D.K Pradhan, “Using Memristor State Change Behavior to Identify Faults in Photovoltaic Arrays, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amstradam, 2014.
  • Sun, Luo, Jimson Mathew, S Rishad A., Pradhan, D.K. and Li, Zhen A low power and robust carbon nanotube 6T SRAM design with metallic tolerance. In, Design Automation and Test in Europe (DATE), Dresden, DE, 24 - 28 Mar 2014.
  • Yuanfan Yang, Jimson Mathew, Marco Ottavi, Salvatore Pontarelli, Dhiraj K. Pradhan:
  • 2T2M memristor based TCAM cell for low power applications. DTIS 2015: 1-6
  • B. Mondal, C. Bandyopadhyay, Jimson Mathew, and H. Rahaman, "Diagnosis of SMGF in ESOP Based Reversible Logic Circuit” IEEE International Symposium on Electronic System Design (ISED) 2014.
  • A. Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: Write scheme for multiple Complementary Resistive Switch (CRS) cells. PATMOS 2014: 1-5
  • J. Jacob, B. R. Jose, Jimson Mathew, "Spectrum Prediction in Cognitive Radio Networks: A Bayesian Approach. NGMAST 2014: 203-208
  • Y.Yang, Jimson Mathew, Rishad A., Pradhan, D.K. “Complementary Resistive Switch Based Stateful LogicOperations Using Material Implication. In, Design Automation and Test in Europe (DATE), Dresden, DE, 24 - 28 Mar 2014.
  • M.Huang, Jimson Mathew R. A. Shafik, , Dhiraj Pradhan, “A Fast and Effective DFT for Test and Diagnosis of Power Switches in SOCs”, IEEE/ACM Confernece on Design, Automation and Test in Europe (DATE 2013).
  • Sabarinath, J. Prakash, B. R. Jose, Jimson Mathew, Overloading Prediction in Symmetric Cross Coupled Low-Pass Sigma Delta Modulators, Procedia Computer Science, Volume 46, 2015, Pages 1223-1229, ISSN 1877-0509, http://dx.doi.org/10.1016/j.procs.2015.01.037. (http://www.sciencedirect.com/science/article/pii/S1877050915000381)
  • .V. Ansel, A.V. J Prakash, B. R. Jose, Jimson Mathew, Enhanced Noise Shaping based Band-Pass Cross-Coupled ΣΔ Modulators for Advanced Wireless Transceivers, Procedia Computer Science, Volume 46, 2015, Pages 1254-1260, ISSN 1877-0509, http://dx.doi.org/10.1016/j.procs.2015.01.044. (http://www.sciencedirect.com/science/article/pii/S1877050915000459)
  • J. Jacob, B. R. Jose, Jimson Mathew, A Fuzzy Approach to Decision Fusion in Cognitive Radio, Procedia Computer Science, Volume 46, 2015, Pages 425-431, ISSN 1877-0509, http://dx.doi.org/10.1016/j.procs.2015.02.040. (http://www.sciencedirect.com/science/article/pii/S1877050915001040)
  • 4. P.V. Anuradha, B R Jose, Jimson Mathew, Improved Segmentation of Suspicious Regions of Masses in Mammograms by Watershed Transform, Procedia Computer Science, Volume 46, 2015, Pages 1483-1490, ISSN 1877-0509, http://dx.doi.org/10.1016/j.procs.2015.02.068. (http://www.sciencedirect.com/science/article/pii/S1877050915001325)
  • Badan, M., Bhattacharjee, S., Rishad A., Jimson Mathew,and Pradhan, Dhiraj K. (2013) Lifetime reliability aware checkpointing mechanism: modelling and analysis. In, IEEE International Symposium on Electronic System Design (ISED), Singapore, SG, 12 - 13 Dec 2013.
  • Reddy, B.K., Sabbavarapu, S., Gupta, K., Prabhat, R., Acharyya, A., Shafik, R.A. and Mathew, J. (2013) A novel and unified digital IC design and automation methodology with reduced NRE cost and time-to-market. In, IEEE International Symposium on Electronic System Design (ISED), Singapore, SG, 12 - 13 Dec 2013.
  • S. Luo,Jimson Mathew, , Shafik, Rishad A. and Pradhan, Dhiraj K. (2013) Low power and robust binary tree SRAM design for embedded systems. In, IEEE International Symposium on Electronic System Design (ISED), Singapore, SG, 12 - 13 Dec 2013.
  • Gang, Li, Jimson Mathew, Pradhan, Dhiraj "Multinomial Memristor Model for Simulations and Analysis" In, IEEE International Symposium on Electronic System Design (ISED), Singapore, SG, 12 - 13 Dec 2013.
  • Sengupta, M. ; Mandal, J.K. ; Jimson Mathew. G-Let Based Authentication/Secret Message Transmission (GASMT) In, IEEE International Symposium on Electronic System Design (ISED), Singapore, SG, 12 - 13 Dec 2013.
  • P. Yeolekar, R. A. Shafik, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, “STEP: A Unified Design Methodology for Secure Test and IP Core Protection. 21st ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), , 2012 , pp. 333–338. May 2012.
  • R. A. Shafik, B. M. Al-Hashimi, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework. 1th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 189–194. June 2012.
  • S. Banerjee, Jimson Mathew, Dhiraj Pradhan, S.P. Mohanty, Variation-Aware TED- Based Approach for Nano-CMOS RTL Leakage Optimization. IEEE 24th International Conference on VLSI Design. ISSN 1063-8210. January 2011.
  • Jimson Mathew, P. Mahesh, A. M Jabir, D. K. Pradhan, and S. Mohanty, “Multiple bits Error Detection and Correction in GF Arithmetic Circuits”, IEEE International Symposium on Electronic System Design (ISED) 2010.
  • Luo Sun, Jimson Mathew, Dhiraj Pradhan, Saraju Mohanty, Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits. IEEE International Symposium on Electronic System Design (ISED), pp. 194–1999. December 2011
  • Hosseinabady, M, Jimson Mathew, Mohanty, Dhiraj Pradhan, Single-Event Transient Analysis in High Speed Circuits. International Symposium on Electronic System Design (ISED), 2011 , pp. 112–117. December 2011.
  • M. Poolakkaparambil, Jimson Mathew, A. Jabir, D. K. Pradhan, and S. P. Mohanty, “BCH Code Based Multiple Bit Error Correction in Finite Field Multiplier Circuits”, in Proceedings of the 12th IEEE International Symposium on Quality Electronic Design (ISQED), 2011.
  • Jimson Mathew, H. Rahaman, A. Jabir, S. P. Mohanty, and D. K. Pradhan, "On the Design of Different Concurrent EDC Schemes for S-box and GF(P)", in Proceedings of the 11th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 211-218, 2010.
  • L. Sun, Jimson Mathew, D. K. Pradhan, and S. P. Mohanty, “Algorithms for Rare Event Analysis in Nano-CMOS Circuits Using Statistical Blockade”, in Special Session on New Horizons in SoC and ASIC Design, Proceedings of the International SoC Design Conference (ISOCC), pp. 162--165, 2010.
  • S. Banerjee, Jimson Mathew , D. K. Pradhan, S. Mohanty and M. Ciesielski, “Variation-Aware TED- Based Approach for Nano-CMOS RTL Leakage Optimization”, 24th International Conference on VLSI Design, 2011, 2-7 Jan., 2011.
  • Jimson Mathew, A. M. Jabir, D. K. Pradhan, and S. Mohanty, “Synthesis of Attack Tolerant Cryptographic Hardware Implementation”, In the Proceedings of 18th IEEE/IFIP International Conference on VLSI and System-On-Chip 2010.
  • S. Banerjee, Jimson Mathew , D. K. Pradhan, S. Mohanty and M. Ciesielski, “A Taylor Expansion Diagram Approach for Nano-CMOS RTL Leakage Optimization” at International Symposium on Electronic System Design (ISED) 2010.
  • S. Banerjee, Jimson Mathew, D. K. Pradhan, and S. Mohanty, “Layout-Aware Illinois Scan Design for High Fault Coverage”, In the Proceedings of International Symposium on Quality Electronic Design (ISQED), 2010.
  • A. Abutaleb, Jimson Mathew, D. K. Pradhan and T. Kocak, “/A Novel Fault Diagnosis Technique in Wireless Sensor Networks/”, The International Journal On Advances in Networks and Services, February 2010.
  • Anas Abu Taleb, Jimson Mathew and D. K. Pradhan, “/Fault Diagnosis in Multi Layered De Bruijn Based Architectures for Sensor Networks/”, 6^th IEEE Int Workshop on Sensor Networks and Systems for Pervasive computing/ (PerSeNs 2010)/ 2010.
  • Anas Abu Taleb, Jimson Mathew and D. K. Pradhan, “Clustered De Bruijn Multi Layered Architectures for Sensor Networks,” The second International conference on Wireless and Mobile Networks, Turkey 2010.
  • Anas Abu Taleb, Jimson Mathew and D. K. Pradhan, “/Efficient Fault Tolerant De Bruijn Based Design Approach for Sensor Networks/”, 4^th International Conference on Sensor Technologies and Applications, 2010. SENSORCOMM ‘10, Italy, July 2010.
  • J. Singh, Jimson Mathew, D.K Pradhan, S. Mohanty, “Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems” IEEE/ACM Conference on Design, Automation and Test in Europe (DATE 2009), Munic, Germany, 2009.
  • J. Singh, Jimson Mathew, D.K Pradhan, S. Mohanty, “Analysis of for Low-Vdd, High-Speed Embedded Systems” IEEE International Conference on VLSI Design, New Delhi, 2009.
  • H. Rahaman, Jimson Mathew, A. Jabir, D. Pradhan, 2009. C-Testable S-Box Implementation for Secure Advanced Encryption Standard. Proc. IEEE On-Line Testing Symposium (IOLTS'08), Sesimbra-Lisbon, Portugal.
  • J. Singh, Jimson Mathew, D.K Pradhan, S. Mohanty, “Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems” IEEE/ACE Confernece on Design, Automation and Test in Europe (DATE 2009), Munic, Germany, 2009.
  • J. Singh, Jimson Mathew, D.K Pradhan, S. Mohanty, “Analysis of for Low-Vdd, High-Speed Embedded Systems” IEEE International Conference on VLSI Design, New Delhi, 2009.
  • Jimson Mathew, D.K. Pradhan " Design Techniques for Bit-Parallel Galois Field Multipliers with Online Single Error Correction and Double Error Detection, IEEE International Online Testing Symposium (IOLTS) 2008 .
  • Jimson Mathew, J. Singh, D.K. Pradhan " Fault Tolerant Reversible Finite Field Arithmetic Circuits, IEEE International Online Testing Symposium (IOLTS) 2008.
  • B.R. Jose, Mythili P. Jimson Mathew, R. Remesan “GA-based Optimization of a Fourth-order Sigma-delta Modulator for WLAN”, IEEE International Conference on Systems, Man, and Cybernetics (SMC 2008), Singapore.
  • R. REMESAN, Muhammad A SHAMIM, Dawei HAN, Jimson Mathew, “ANFIS and NNARX based Rainfall-Runoff Modeling” IEEE International Conference on Systems, Man, and Cybernetics (SMC 2008), Singapore.
  • J. Singh, Jimson Mathew, D.K Pradhan “A Subthreshold Single Ended I/O SRAM Cell Design for Nanometer CMOS Technologies”, In: 20th IEEE International System On Chip Conference (IEEE SOCC 2007), September 2087.
  • Jimson Mathew, J. Singh, D.K. Pradhan "Fault Tolerant Bit Parallel Finite Field Multipliers Using LDPC Codes" ISCAS 2008..
  • J. Singh, Jimson Mathew, D.K. Pradhan “A Nano-CMOS Process Variation Induced Read Failure Tolerant SRAM Cell” ISCAS 2008 .
  • Jimson Mathew, D. K. Pradhan et al. “Single Error Correcting Finite Field Multipliers over GF(2^m), VLSI Design, 2008.
  • Jimson Mathew, D. K. Pradhan et al. “A Galois Field Based Logic Synthesis Approach with Testability, VLSI Design, 2008.
  • Jimson Mathew, D. K. Pradhan et al. “Design of Reversible Finite Field Arithmetic Circuits with Error Detection, VLSI Design, 2008.
  • M.Hosseinabady, Jimson Mathew and D. K Pradhan"De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs" IEEE/ACE Confernece on Design, Automation and Test in Europe (DATE 2008), Munic, Germany, 2008.
  • Jimson Mathew, D. K. Pradhan, “Area efficient pseudo parallel Galois field Multiplier”, IEEE Norchip Conference, 2007.
  • Jimson Mathew, H. Rahaman, Dhiraj K. Pradhan: Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. IOLTS 2007: 207-208.
  • Jimson Mathew, R. Mahesh. A.P Vinod and L. Edmund, “Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Software Radio Receivers” Sixth IEEE International Conference on Information, Communications & Signal Processing (ICICS'07) Singapore, December 2007, Singapore.
  • B. R. Jose, Jimson Mathew, P. Mythili, “Wideband Low-Distortion Sigma-Delta ADC for WLAN” Sixth IEEE International Conference on Information, Communications & Signal Processing (ICICS'07) Singapore, December 2007, Singapore.
  • T. Makkiel, Jimson Mathew, D.K Pradhan, “Soft-Error induced System-Failure Rate Analysis in an SoC”, IEEE Norchip 2007.
  • J. Singh, Jimson Mathew and D. K. Pradhan, “Statistical Analysis of Steady State Leakage Currents in Nano-CMOS Devices” IEEE Norchip Conference 2007.
  • M. Hosseinabady, M. Reza, Jimson Mathew and Dhiraj Pradhan, "Reliable Network-on-Chip Based on Generalized de Bruijn Graph" In: IEEE International High Level Design Validation and Test Workshop(HLDVT), IEEE, November 2007.
  • B. R. Jose, Jimson Mathew, P. Mythili and Dhiraj Pradhan. A Triple-Mode Feed-Forward Sigma-Delta Modulator Design For GSM / WCDMA / WLAN Applications. In: 20th IEEE International System On Chip Conference (IEEE SOCC 2007), September 2007.
  • H. Zarandi, S. G. Miremadi, Dhiraj Pradhan and Jimson Mathew. CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. In: IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA, IEEE, May 2007.
  • M. Hosseinabady, Jimson Mathew and Dhiraj Pradhan. Application of de Bruijn graphs to NoC design. In: Design Automation and Test in Europe Workshops, DATE07-WKS , pages 111--116. IEEE/ACM, March 2007.
  • H. Rahaman, Jimson Mathew, Dhiraj Pradhan and A.M. Jabir. Easily Testable Implementation for Bit Parallel Multipliers in GF(2m). In: IEEE International High Level Design Validation and Test Workshop(HLDVT), IEEE, November 2006.
  • H. Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). VLSI Design 2007: 479-484.
  • Jimson Mathew, Koushik Maharatna and Dhiraj Pradhan. A Low Power 128-Pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks. In: IEEE PRIME Conference, pages 377--380. IEEE, June 2006.
  • Jimson Mathew, Koushik Maharatna and Dhiraj Pradhan. Exploration of Power optimal Implementation Technique of 128-Pt FFT/IFFT for WPAN using Pseudo- Parallel Datapath Strcuture. In: IEEE International Conference on Communication Systems, Singapore, IEEE, February 2006.
  • H. Rahaman, Jimson Mathew, B. K. Sikdar, Dhiraj K. Pradhan: Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430.
  • Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ISCAS 2007: 141-144.
  • R. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan: On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ISCAS 2007: 3002-3005.
  • Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew: An efficient technique for synthesis and optimization of polynomials in GF(2m). ICCAD 2006: 151-157
  • Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. ISQED 2007: 380-385.
  • Costas Argyrides, Jimson Mathew, Ahmad Al-Yamani and Dhiraj Pradhan. Performance Analysis of an Error Tolerant Low Power Memory Architecture. In: IEEE International Design and Test Workshop, November 2006.
  • A. Singh, Jimson Mathew, A. M. Jabir and Dhiraj Pradhan, “An efficient Synthesis approach with Testability”, IEEE International Design and Test Workshop, November 2006.
  • Jimson Mathew, J. Thomas, and E. Dubrova. Two fault tolerant MIPS processor architectures for NOC applications. In Proceedings of NORCHIP'03, Riga, Latvia, November 2003.
  • Jimson Mathew and E. Dubrova. Totally self-checking 1-out-of-n checker with application to the design of fault tolerant FIR filter. In Proceedings of Proceedings of the International Workshop on the Applications of the Reed-Muller Expansion in Circuit Design, Trier, Germany, March 2003.
  • Jimson Mathew, E. Dubrova, and H. Tenhunen. Electronic nanotechnology based on non-binary principles. In Proceedings of International Nanotechnology Conference, San Francisco, California USA, February 2003.
  • Jimson Mathew and E. Dubrova. Totally self-checking 1-out-of-n checker with application to fault tolerant design. In Proceedings of NORCHIP'02, Copenhagen, Denmark, November 2002.
  • Jimson Mathew and E. Dubrova. Self-checking checker for 1-out-of-n code based on current-mode CMOS logic. In Proceedings of Defect and Fault Tolerance in VLSI Systems Conference, DFT2002, Vancouver, Canada, November 2002.
  • Jimson Mathew and E. Dubrova. A novel 1-out-of-n differential cmos checker and its applications to fault tolerant designs. In Proceedings of Baltic Electronics Conference, Tallinn, Estonia, October 2002.
  • E. Dubrova, Y. Jamal, and Jimson. Mathew. Non-silicon non-binary computing: Why not? In Proceedings of 1st Workshop on Non-Silicon Computation, pages 23-29, Boston, USA, February 2002.
  • Jimson Mathew, D. Radhakrishnan, "Fast Residue-to-Binary Converter Architectures," 42nd Midwest Symposium on Circuits and Systems to be held at New Mexico State University in Las Cruces, USA, August 8-11,1999.
  • Jimson Mathew, D. Radhakrishnan and T. Srikanthan, "Residue-to-Binary Arithmetic Converter for the set 2n-1, 2n, 2n+1, 2n+1-1," 1999 IEEE-EURASIP Workshop on Nonlinear Signal and Image Processing (NSIP'99), 20-23 June, pp. 190-193, 1999.
  • Jimson Mathew, D. Radhakrishnan and T. Srikanthan, "New Area Efficient Residue-to-weighted Number System Converters", 6th IEEE International Conference on Circuits and Systems, (ICECS 99), Cyprus, September 1999.
  • Jimson Mathew, D. Radhakrishnan, T. Srikanthan and A. P. Preethy, "A Low overhead Reverse Converter for Fault tolerant RNS," International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 99, Japan, July 1999.
  • D. Radhakrishnan, T. Srikanthan and Jimson Mathew, "Using the 2n property to make an area efficient Residue-to-Binary Converter," International Symposium on Signals, Circuits and Systems (SCS 99), Lasi, Romania, July 6-7, 1999.
  • Jimson Mathew, D. Radhakrishnan, and T. Srikanthan, "Memoryless Residue-to-Mixed Radix Converter," European Conference on Circuit Theory and Design ECCTD '99 August 1999 Stresa, Italy, 1999.
  • Jimson Mathew, D. Radhakrtishnan and T. Srikanthan, "Memoryless Residue-to-Mixed Radix converter with Totally Self Checking error Detection," 8th international symposium on integrated circuits, devices & systems (ISIC-99) September8–10, Grand Hyatt, Singapore, 1999.
  • Jimson Mathew D. Radhakrishnan and T. Srikanthan, "A High Speed RNS FIR Digital Filter Architecture with Totally Self-Checking Code Error Detection," Second International Conference on Information, Communications & Signal Processing (ICICS'99) Singapore, December 1999, Singapore.
  • Jimson Mathew, D. Radhakrishnan and T. Srikanthan, "Residue-to-binary arithmetic converter for the moduli set {2n+1, 2n, 2n –1, 2n+1+1, 2n+2-1}," International Conference on Signal Processing Applications & Technology, ICSPAT November 1-4, 1999 Orlando, Florida, USA.
  • Jimson Mathew, Young Weng Ho and M. Jian “An RNS Based Approach to the Design of Filter Bank Channeliser for Base Station Receivers”- Eleventh Annual Int'l Conf. Signal Processing Applications and Technology, Dallas, Texas, USA. Oct. 2000.
  • Jimson Mathew and D. Radhakrishnan, An FIR Digital Filter Using One-Hot Coded Residue Representation, The European Signal Processing Conference (EUSIPCO-2000), Tampere, Finland, Oct. 2000.
Presentations Keynote: Fourth International Conference on Eco-friendly Computing and Communication Systems (ICECCS) 7-8 December 2015,National Institute of Technology, Kurukshetra, India

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