1. Science and Engineering Research Board (SERB) DST Govt. of India, “Exploration of 8/9 nano-meter process variation immune doping- and junction-free devices and their circuits", ~35,00,000/- (PI, 2017-2019).

2. Science and Engineering Research Board (SERB) DST Govt. of India, “Design and Development of RF Energy Harvesting Circuits for Low-power    Electronic Devices ", ~55,00,000/- (PI, 2015-2018).

3. Jawar Singh and Chitrakant Sahu, “Nano-CMOS and Post-CMOS Electronics: Devices and Modelling, [Junction and Doping Free Transistors For Future Computing]", IET UK, ISBN 978-1-84919-997-1, 2015.

2. Jawar Singh and Balwinder Raj, “Embedded System Book 1 Chapter Title [SRAM Cells for Embedded Systems]", INTECH Open Access Publisher, ISBN 979-953-307-580-7, 2014.

1. Jawar Singh, S. Mohanty and Dhiraj K. Pradhan, “Robust and Power-Aware SRAM Bitcell Design and Analysis", Springer-Verlag New York Inc., Hardcover, ISBN 978-1-4614-0817-8, 2013.

3. Dhiraj K. Pradhan, Jawar Singh and Jimson Mathew, “Static Random Access Memory", US Patent No. 7706174; issued April 27, 2010.

2. Jawar Singh Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, and Vijay Krishnan Narayan, “TFET based 6T SRAM cell ", U.S. Patent No. 8,369,134, Feb 3, 2013.

1. Jawar Singh and Anup Shrivastav, “Resistive Switching Device: Memristor", Indian Patent Application No. 431/MUM/2015, Feb 2015.

28. N. Kamal, M. Panchore and J. Singh, "3-D Simulation of Junction- and Doping-free Field-effect Transistor under Heavy Ion Irradiation," IEEE Transactions on Device and Materials Reliability, March 2018.

27. Lokesh Kumar Bramhane, and Jawar Singh, “Improved performance of bipolar charge plasma transistor by reducing the horizontal electric eld", Superlattices and Microstructures (Elsevier), Vol 104, April 2017, (IF 2.13).

26. Muhammad Khalid, Jawar Singh and Saraju P. Mohanty, “Impact of Channel Hot Carrier Effect in Junction- and Doping-Free Devices and Circuits", Journal of Nanoelectronics and Optoelectronics, vol.12, no.1, Jan 2017.

25. Meena Panchore, Jawar Singh and Saraju P. Mohanty, “Impact of Channel Hot Carrier effect in Junction- and Doping-Free Devices and Circuits", IEEE Transactions on Electron Devices, vol.67, no.12, Oct 2016 (IF 2.60).

24. Kanchan Cecil, and Jawar Singh, “Influence of Germanium source on dopingless tunnel-FET for improved analog/RF performance", Superlattices and Microstructures (Elsevier), Vol 96, November 2016 (IF 2.13).

23. Abhishek Sahu, Lokesh Kumar Bramhane and Jawar Singh, “Symmetric Lateral Doping-free BJT: A Novel Design for Mixed Signal Applications", IEEE Transactions on Electron Devices, vol.67, no.7, May 2016 (IF 2.60).

22. Lokesh Kumar Bramhane, and Jawar Singh, “Two-zone SiGe base heterojunction bipolar charge plasma transistor for next generation analog and RF applications", Superlattices and Microstructures (Elsevier), Vol 96, November 2016 (IF 2.13).

21. Avinash Lahgere, Meena Panchore, and Jawar Singh, “Dopingless Ferroelectric Tunnel FET Architecture for the Improvement of Performance of Dopingless n-Channel Tunnel FETs", Superlattices and Microstructures (Elsevier), Vol 96, August 2016 (IF 2.13).

20. Muhammad Khalid and Jawar Singh, “Memristor based unbalanced ternary logic gates", Analog Integrated Circuits and Signal Processing (Springer), Vol 87 (3), pp 339-406, 2016.

19. Vishwas Shrivastava, Anup Kumar, Chitrakant Sahu and Jawar Singh, “Temperature sensitivity analysis of dopingless charge-plasma transistor", Solid-State Electronics (Elsevier), November 2015, ISSN 0038-1101 (IF 1.50).

18. Deep Kishore Parsediya, Jawar Singh and Pavan Kumar Kankar, “Variable width based stepped MEMS cantilevers for micro or pico level biosensing and effective switching", Journal of Mechanical Science and Technology (Springer), Vol 29, n0. 11, pp 4823-4832, Nov 2015, 1976-3824 (IF 0.84).

17. Chitrakant Sahu and Jawar Singh, “Scalability and Process Induced Variation Analysis of Polarity Controlled Silicon Nanowire Transistor", Journal of Computational Electronics (Springer), August 2015 (IF 1.52).

16. Avinash Lahgere, Chitrakant Sahu and Jawar Singh, “PVT Aware Design of Dopingless Dynamically Congurable Tunnel-FET", IEEE Transactions on Electron Devices, vol.62, no.8, August 2015 (IF 2.60).

15. Chitrakant Sahu and Jawar Singh, “Potential Benefits and Sensitivity Analysis of doping-less Transistor for Low Power Applications", IEEE Transactions on Electron Devices, vol.62, no.3, pp.729,735, March 2015 (IF 2.60).

14. Sunil Pandey and Jawar Singh, “A low power and high gain CMOS LNA for UWB applications in 90nm CMOS process", Microelectronics Journal (Elsevier), Volume 46, Issue 5, May 2015, Pages 390-397 (IF 0.91).

13. Avinash Lahgere, Chitrakant Sahu and Jawar Singh, “An Electrically Doped Dynamically Configurable Field Effect Transistor for Low Power and High Performance Applications", Electronics Letters, IET-UK (August 2015) (IF 1.15).

12. LK Bramhane, N Upadhyay, JR Veluru and Jawar Singh, “Symmetric bipolar charge-plasma transistor with extruded base for enhanced performance", Electronics Letters, IET-UK (June 2015) (IF 1.15).

11. Sunil Pandey and Jawar Singh, “A 0.6V low-power and high-gain ultra-wideband low-noise amplier with forward-body-bias technique for low-voltage operations", IET-UK Microwaves, Antennas & Propagation, Volume 9, Issue 8, pp 728 - 734 2015, (IF 0.91).

10. Chitrakant Sahu and Jawar Singh, “Charge-Plasma Based Process Variation Immune Junctionless Transistor", Electron Device Letters, IEEE, Volume 35, Issue 3, pp 411 - 413, 2014/3 (IF 3.05).

9. Chitrakant Sahu, Ajanta Ganguly and Jawar Singh, “Design and Performance Projection of Symmetric Bipolar Charge-plasma Transistor on SOI", IET-UK, Electronics Letters, IET-UK (Sept. 2014) (IF 1.15).

8. Anup Shrivastava, Komal Singh and Jawar Singh, “Improved Dual Sided Doped Memristor: Modeling and Applications", IET-UK, Journal of Engineering (April 2014).

7. Deep Kishore Parsediya, Jawar Singh and Pavan Kumar Kankar, “Simulation and Analysis of Highly Sensitive MEMS Cantilever Designs for in vivo Label Free" Biosensing", Elsevier, Vol 14, Journal Procedia Technology, 2014/12/31.

6. Chitrakant Sahu and Jawar Singh, “Device and Circuit Performance Analysis of Double Gate Junctionless Transistors at Lg=18nm", IET-UK, Journal of Engineering (Feb 2014).

5. Chitrakant Sahu, Pragya Swami, S Sharma and Jawar Singh, “Simplified Drain Current Model for Pinchoff Double Gate Junctionless Transistor", IET-UK, Electronics Letters, IET-UK, Jan 2014, V 50/2 (IF 1.15).

4. Jawar Singh and N. Vijaykrishnan, “A highly reliable NBTI Resilient 6T SRAM cell", Microelectronics Reliability (Elsevier), Volume 53, Issue 4, April 2013, Pages 565-572, ISSN 0026-2714 (IF 1.28).

3. Saraju P. Mohanty, Jawar Singh, Elias Kougianos, and Dhiraj K. Pradhan, “Statistical DOE-ILP Based Power-Performance-Process P3) Optimization of Nano-CMOS SRAM", Integration, the VLSI Journal (Elsevier), Volume 45, Issue 1, January 2012, Pages 33{45, ISSN 0167-9260 (IF 0.72).

2. Jawar Singh, Dhiraj K. Pradhan, Simon Hollis and Saraju P. Mohanty, “A single ended 6T SRAM cell design for ultra-low-voltage applications", Journal of Institute of Electronics, Information and Communication Engineers (IEICE), Japan, Vol. 5 (2008), No. 18 pp. 750-755.

1. Jawar Singh and R.S Anand, “Computer aided analysis of phonocardiogram", Journal of Medical Engineering & Technology, 2007, Vol. 31, No. 5 , Pages 319-323.